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7.2.4
Bus Control Register H (BCRH)
Bit
:
ICIS1
Initial value
:
R/W
:
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
Description
0
Idle cycle not inserted in case of successive external read cycles in different areas
1
Idle cycle inserted in case of successive external read cycles in different areas
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
Description
0
Idle cycle not inserted in case of successive external read and external write cycles
1
Idle cycle inserted in case of successive external read and external write cycles
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface.
Bit 5
BRSTRM
Description
0
Area 0 is basic bus interface
1
Area 0 is burst ROM interface
142
7
6
ICIS0
BRSTRM
1
1
R/W
R/W
5
4
BRSTS1
BRSTS0
0
1
R/W
R/W
3
2
RMTS2
RMTS1
0
0
R/W
R/W
1
0
RMTS0
0
0
R/W
R/W
(Initial value)
(Initial value)
(Initial value)
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