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DDCSWR
SAR
Bit 6
Bit 0
SW
FS
0
0
1
1
—
18.2.3
Second Slave Address Register (SARX)
Bit
:
SVAX6
Initial value :
R/W
:
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
SVAX0, differing from the addresses of other slave devices connected to the I
700
SARX
Bit 0
FSX
Operating Mode
0
I
•
1
I
•
•
0
I
•
•
1
Synchronous serial format
•
—
Must not be set.
7
6
SVAX5
SVAX4
0
0
R/W
R/W
2
C bus format
SAR and SARX slave addresses recognized
2
C bus format
SAR slave address recognized
SARX slave address ignored
2
C bus format
SAR slave address ignored
SARX slave address recognized
SAR and SARX slave addresses ignored
5
4
SVAX3
SVAX2
0
0
R/W
R/W
3
2
SVAX1
SVAX0
0
0
R/W
R/W
2
C bus.
(Initial value)
1
0
FSX
0
1
R/W
R/W
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