Hitachi H8S/2633 Hardware Manual page 889

Sub-Sleep Mode

Sub-Sleep Mode

When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,

and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode.

In sub-sleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0,

and WDT1 are also stopped. The contents of the CPUís internal registers, the data in internal

RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, and 14-bit

PWM) and I/O ports are retained.

Exiting Sub-Sleep Mode

Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or

IRQ0 to IRQ7), or signals at the RES, MRES, or STBY pins.

(1) Exiting Sub-Sleep Mode by Interrupts

When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts.

In the case of IRQ0 to IRQ7 interrupts, sub-sleep mode is not cancelled if the corresponding

enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting

modules, the interrupt enable register has been set to disable the reception of that interrupt, or is

masked by the CPU.

(2) Exiting Sub-Sleep Mode by RES or MRES Pins

For exiting sub-sleep mode by the RES or MRES pins, see (2), Exiting Software Standby Mode by

RES or MRES pins in Section 24.6.2, Exiting Software Standby Mode.

(3) Exiting Sub-Sleep Mode by STBY Pin

When the STBY pin level is driven low, a transition is made to hardware standby mode.