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TSTR—Timer Start Register
Bit
:
Initial value
:
R/W
:
TSYR—Timer Synchro Register
Bit
:
Initial value
:
R/W
:
1064
7
6
—
—
CST5
0
0
—
—
R/W
Counter start 5 to 0
0
TCNTn counting operation disabled.
1
TCNTn counting operation enabled.
Note: When the TIOC pin is operating as an output pin, writing 0 to a CST bit
disables counting. The TIOC pins output compare output level is maintained.
When a CST bit is 0, the output level of the pin is updated to the set initial
output value by writing to TIOR.
7
6
—
—
SYNC5
0
0
—
—
R/W
Timer sync 5 to 0
0
TCNTn operate independently (TCNTs are preset and cleared
independently of other channels)
1
TCNTn operate in sync mode. Synchronized
TCNT presetting and clearing enabled.
Note:
1.
The SYNC bit of a minimum of two channels must be set to 1 in order to
select sync operation.
2.
To enable sync clearing, in addition to the SYNC bits, the TCR CCLR2 to
CCLR0 bits must be set for the TCNT clearing factors.
H'FEB0
5
4
CST4
CST3
0
0
R/W
R/W
H'FEB1
5
4
SYNC4
SYNC3
0
0
R/W
R/W
3
2
CST2
CST1
0
0
R/W
R/W
3
2
SYNC2
SYNC1
0
0
R/W
R/W
TPU Common
1
0
CST0
0
0
R/W
(n= 5 to 0)
TPU Common
1
0
SYNC0
0
0
R/W
(n= 5 to 0)
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