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17.2.2
Serial Status Register (SSR)
Bit
:
TDRE
Initial value :
R/W
:
R/(W)*
Note: * Only 0 can be written, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
Bit 4
ERS
Description
0
Normal reception, with no error signal
[Clearing conditions]
•
Upon reset, and in standby mode or module stop mode
•
When 0 is written to ERS after reading ERS = 1
1
Error signal sent from receiver indicating detection of parity error
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
666
7
6
RDRF
ORER
1
0
R/(W)*
R/(W)*
5
4
ERS
PER
0
0
R/(W)*
R/(W)*
3
2
TEND
MPB
0
1
R
1
0
MPBT
0
0
R
R/W
(Initial value)
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