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Increment
address
Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1 and 2. More than 2 bits cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
812
Start
Set SWE1 bit in FLMCR1
Wait (x) µs
tsswe:
n = 1
Set EBR1 and 2
Enable WDT
Set ESU1 bit in FLMCR1
Wait (y) µs
tsesu:
Set E1 bit in FLMCR1
tse:
Wait (z) ms
Clear E1 bit in FLMCR1
Wait (α) µs
tce:
Clear ESU1 bit in FLMCR1
Wait (β) µs
tcesu:
Disable WDT
Set EV1 bit in FLMCR1
Wait (γ) µs
tsev:
Set block start address to verify address
H'FF dummy write to verify address
Wait (ε) µs
tsevr:
Read verify data
Verify data = all "1"?
OK
NG
Last address of block?
OK
Clear EV1 bit in FLMCR1
Wait (η) µs
tcev:
*4
End of
NG
erasing of all erase
blocks?
OK
Clear SWE1 bit in FLMCR1
Wait (× 1) µs
tcswe:
End of erasing
Figure 22-12 Erase/Erase-Verify Flowchart
*1
*3
Start erase
Halt erase
*2
NG
Clear EV1 bit in FLMCR1
tcev:
Clear SWE1 bit in FLMCR1
tcswe:
n ← n + 1
Wait (η) µs
NG
n ≥ (N)?
OK
Wait (× 1) µs
Erase failure
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