Hitachi H8S/2633 Hardware Manual page 478

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 11-5 shows the register combinations used in buffer operation.

Table 11-5 Register Combinations in Buffer Operation

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 11-16.

Buffer register

Timer General Register

Compare match signal

Timer general

Figure 11-16 Compare Match Buffer Operation

Buffer Register