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TSR1—Timer Status Register 1
TSR2—Timer Status Register 2
TSR4—Timer Status Register 4
TSR5—Timer Status Register 5
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
Initial value
R/W
Underflow flag
Count direction flag
0
1
Input capture/output compare flag B
Note: Only 0 can be written to these bits (to clear these flags).
:
7
6
TCFD
—
:
1
1
:
R
—
0
0
[Clearing]
Writing 0 to TCFU after reading TCFU=1.
1
[Setting]
When the TCNT value underflows (H'0000 → H'FFFF).
TCNT counts down.
TCNT counts up.
Overflow flag
0
0
[Clearing]
Writing 0 to TCFV after reading TCFV=1.
1
[Setting]
When the TCNT value overflows (H'FFFF → H'0000).
0
[Clearing]
(1) When the DTC is started by a TGIB interrupt and the DTC MRB DISEL
bit is 0;
(2) Writing 0 to TGFB after reading TGFB=1.
1
[Setting]
(1) When TGRB is functioning as the output compare register and TCNT=
TGRB;
(2) When TGRB is functioning as the input capture register and the value
of TCNT is sent to TGRB by the input capture signal.
Input capture/output compare flag A
0
[Clearing]
(1) When the DTC is started by a TGIA interrupt and the DTC MRB DISEL
bit is 0;
(2) When the DMAC is started by a TGIA interrupt and the DMAC DMABCR
DTA bit is 1;
(3) Writing 0 to TGFA after reading TGFA=1.
1
[Setting]
(1) When TGRA is functioning as the output compare register and TCNT=
TGRA;
(2) When TGRA is functioning as the input capture register and the value
of TCNT is sent to TGRA by the input capture signal.
H'FF25
H'FF35
H'FE95
H'FEA5
5
4
3
TCFU
TCFV
—
0
0
0
R/(W)*
R/(W)*
—
2
1
0
—
TGFB
TGFA
0
0
0
—
R/(W)*
R/(W)*
TPU1
TPU2
TPU4
TPU5
1063
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