Hitachi H8S/2633 Hardware Manual page 913

ø
A23 to A0
CS5 to CS2
(RAS)
CAL, LCAS
(RCTS=0)
CAL to LCAS
(When RCTS is set to 1)
(read)
OE
(When OES is set to 1)
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
ø
CS5 to CS2
(RAS)
CAS, LCAS
900
T
p
t
AD
t
AS
t
PCH
t
CSD2
Figure 25-11 DRAM Access Timing
TR TR
p r
t
CSR
t
CASD1
Figure 25-12 DRAM CBR Refresh Timing
T r T
C1
t
AD
t
AH
t
ACC4
t
CASD1
t
CASD2
t
OED2
t
ACC3
t
WRD1
t
WCS
t
t
WDD
TR
C1
t
CSD2
T
C2
t t
ACC1 CASD1
t t
ACC2 CASD1
t
ACC2
t
RDS
t
WRD1
t
WCH
t
WDS WDH
TR
C2
t
CSD
t
CP1
t
CP2
t
OED1
t
RDH
t
CSD1
t
CASD1