Advertisement
BCRA—Break Control Register A
BCRB—Break Control Register B
Bit
:
Initial value
:
R/W
:
Condition match flag A
0
1
Break address mask register A2 to A0
BAMRA
BAMRA
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Notes: The bit configuration of BCRB is the same as that of BCRA.
* Only 0 can be written to these bits (to clear these flags).
1030
7
6
CMFA
CDA
0
0
R/(W)*
R/W
CPU cycle/DTC cycle select A
0
When the CPU is the bus master, PC break performed.
1
When the CPU or DTC is the bus master, PC break performed.
[Clearing]
Writing 0 to CMFA after reading CMFA=1.
[Setting]
When channel A conditions are true.
BAMRA
0
0
All bits, without masking BARA, included in break condition.
1
BAA0 (LSB) masked and not included in break condition.
0
BAA1 and BAA0 (low 2 bits) masked and not included in break condition.
1
BAA2 to BAA0 (low 3 bits) masked and not included in break condition.
0
BAA3 to BAA0 (low 4 bits) masked and not included in break condition.
1
BAA7 to BAA0 (low 8 bits) masked and not included in break condition.
0
BAA11 to BAA0 (low 12 bits) masked and not included in break condition.
1
BAA15 to BAA0 (low 16 bits) masked and not included in break condition.
Break condition select
CSELA1
CSELA0
0
0
1
1
H'FE08
H'FE09
5
4
BAMRA2
BAMRA1
BAMRA0
0
0
R/W
R/W
Sets instruction fetch as break condition.
0
Sets data read cycle as break condition.
1
Sets data write cycle as break condition.
0
Sets data read/write cycle as break condition.
1
3
2
CSELA1
CSELA0
0
0
R/W
R/W
R/W
Break interrupt enable
0
Disables PC break interrupt.
1
Enables PC break interrupt.
PBC
PBC
1
0
BIEA
0
0
R/W
Advertisement
