Hitachi H8S/2633 Hardware Manual page 247

Bit 11
DTA1B Description
0 Clearing of selected internal interrupt source at time of DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1A data transfer
factor setting.
Bit 10
DTA1A Description
0 Clearing of selected internal interrupt source at time of DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0B data transfer
factor setting.
Bit 9
DTA0B Description
0 Clearing of selected internal interrupt source at time of DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0A data transfer
factor setting.
Bit 8
DTA0A Description
0 Clearing of selected internal interrupt source at time of DMA transfer is disabled
1 Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the
activation source selected by the data transfer factor setting is ignored. If the activation source is
an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1
222
(Initial value)
(Initial value)
(Initial value)
(Initial value)