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Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
3
0
0
1
1
0
1
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
424
0
0
TGR3D is Output disabled
output
1
compare
0
1
register*
1
0
0
1
1
0
1
0
0
TGR3D is
input
1
capture
*
1
register*
*
*
Initial output is 0
output
2
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD3 pin
2
Capture input
source is channel
4/count clock
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4
count-up/count-down*
*: Don't care
1
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