Hitachi H8S/2633 Hardware Manual page 308

Internal address

Internal read signal

External address

Figure 8-34 Example of Single Address Transfer Using Write Data Buffer Function

When the write data buffer function is activated, the DMAC recognizes that the bus cycle

concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one

state after the start of the DMA write cycle or single address transfer.

DMAC Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B.

Table 8-13 summarizes the priority order for DMAC channels.

Table 8-13 DMAC Channel Priority Order

Short Address Mode

Full Address Mode