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TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
TCR2—Timer Control Register 2
TCR3—Timer Control Register 3
Bit
:
Initial value
:
R/W
:
Clock select 2 to 0
CKS2
0
1
Note: * No countup clock is generated if the channel 0 (channel 2) clock input is the TCNT1
1012
7
6
CMIEB
CMIEA
0
0
R/W
R/W
Timer overflow interrupt enable
0
1
Compare match interrupt enable A
0
CMFA interrupt request (CMIA) disabled
1
CMFA interrupt request (CMIA) enabled
Compare match interrupt enable B
0
CMFB interrupt request (CMIB) disabled
1
CMFB interrupt request (CMIB) enabled
Counter clear 1, 0
CCLR1
CCLR0
0
0
1
1
0
1
CKS1
CKS0
0
0
1
1
0
1
0
0
1
1
0
1
(TCNT3) overflow signal, and that the channel 1 (channel 3) clock input is the TCNT0
(TCNT2) compare match signal. Do not, therefore, attempt to make such a setting.
H'FF68
H'FF69
H'FDC0
H'FDC1
5
4
OVIE
CCLR1
CCLR0
0
0
R/W
R/W
OVF interrupt request (OVI) disabled
OVF interrupt request (OVI) enabled
Clearing disabled
Cleared by compare match A
Cleared by compare match B
Cleared by rising edge of external reset input
Clock input disabled
Internal clock: Counting on falling edge of ø/8
Internal clock: Counting on falling edge of ø/64
Internal clock: Counting on falling edge of ø/8192
Channel 0: Counting on TCNT1 overflow signal *
Channel 1: Counting on TCNT0 compare match A *
Channel 2: Counting on TCNT3 overflow signal *
Channel 3: Counting on TCNT2 compare match A *
External clock: Counting on rising edge
External clock: Counting on falling edge
External clock: Counting on both rising and falling edges
3
2
CKS2
CKS1
0
0
R/W
R/W
R/W
TMR0
TMR1
TMR2
TMR3
1
0
CKS0
0
0
R/W
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