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Interrupt Source
CMIA0 (compare match A0)
CMIB0 (compare match B0)
OVI0 (overflow 0)
Reserved
CMIA1 (compare match A1)
CMIB1 (compare match B1)
OVI1 (overflow 1)
Reserved
DED0A (channel 0/channel 0A
transfer end)
DEND0B (channel 0B transfer end)
DEND1A (channel 1/channel 1A
transfer end)
DEND1B (channel 1B transfer end)
Reserved
ERI0 (receive error 0)
RXI0 (reception completed 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
ERI1 (receive error 1)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
ERI2 (receive error 2)
RXI2 (reception completed 2)
TXI2 (transmit data empty 2)
TEI2 (transmission end 2)
Origin of
Interrupt
Vector
Source
Number
8-bit timer
64
channel 0
65
66
—
67
8-bit timer
68
channel 1
69
70
—
71
DMAC
72
73
74
75
—
76
77
78
79
SCI
80
channel 0
81
82
83
SCI
84
channel 1
85
86
87
SCI
88
channel 2
89
90
91
Vector
Address*
Advanced
Mode
IPR
H'0100
IPRI6 to 4
H'0104
H'0108
H'010C
H'0110
IPRI2 to 0
H'0114
H'0118
H'011C
H'0120
IPRJ6 to 4
H'0124
H'0128
H'012C
H'0130
H'0134
H'0138
H'013C
H'0140
IPRJ2 to 0
H'0144
H'0148
H'014C
H'0150
IPRK6 to 4
H'0154
H'0158
H'015C
H'0160
IPRK2 to 0
H'0164
H'0168
H'016C
Priority
High
Low
103
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