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7.2.7
Memory Control Register (MCR)
Bit
:
TPC
Initial value
:
R/W
:
R/W
The MCR is an 8-bit read/write register that, when areas 2 to 5 are set as the DRAM interface,
controls the DRAM strobe method, number of precharge cycles, access mode, address multiplex
shift amount, and number of wait states to be inserted when a refresh is performed.
The MCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Bit 7—TP Cycle Control (TPC): When accessing areas 2 to 5, allocated to DRAM, this bit
selects whether the precharge cycle (T
Bit 7
TPC
Description
0
Insert 1 precharge cycle.
1
Insert 2 precharge cycles.
Bit 6—Burst Access Enable (BE): This bit enables/disables burst access of areas 2 to 5, allocated
as DRAM space. DRAM space burst access is in high-speed page mode. When using EDO type in
this case, either select OE output or RAS up mode.
Bit 6
BE
Description
0
Burst disabled (always full access).
1
Access DRAM space in high-speed page mode.
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are allocated to DRAM space, this bit
selects whether the RAS signal level remains Low while waiting for the next DRAM access (RAS
down mode) or the RAS signal level returns to High (RAS up mode), when DRAM access is
discontinued.
Bit 5
RCDM
Description
0
DRAM interface: selects RAS up mode.
1
DRAM interface: selects RAS down mode.
7
6
BE
RCDM
0
0
R/W
R/W
) is 1 state or 2 states.
P
5
4
CW2
MXC1
0
0
R/W
R/W
3
2
MXC0
RLW1
0
0
R/W
R/W
1
0
RLW0
0
0
R/W
(Initial value)
(Initial value)
(Initial value)
149
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