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7.5.5
DRAM Interface Pins
Table 7-7 shows the pins used for the DRAM interface, and their functions.
Table 7-7
DRAM Interface Pin Configuration
In DRAM
Pin
Mode
HWR
WE
LCAS
LCAS
CS2
RAS2
CS3
RAS3
CS4
RAS4
CS5
RAS5
CAS
UCAS
WAIT
WAIT
A12 to A0
A12 to A0
D15 to D0
D15 to D0
OE
OE*
Note: * Valid when OES bit set to 1.
7.5.6
Basic Timing
Figure 7-15 shows the basic access timing for DRAM space. There are four basic DRAM timing
states. In contrast to the standard bus interface, the corresponding ASTCR bit only controls the
enabling/disabling of wait insertion and has no effect on the number of access states. When the
corresponding ASTCR bit is cleared to 0, no wait states can be inserted in the DRAM access
cycle.
The four basic timing states are as follows: T
cycle) 1 state, T
and T
c1
174
Name
Write enable
Lower column address
strobe
Row address strobe 2 Output
Row address strobe 3 Output
Row address strobe 4 Output
Row address strobe 5 Output
Upper column address
strobe
Wait
Address pin
Data pin
Output enable pin
(column address output cycle) two states.
c2
Direction
Function
Output
Write enable when accessing
DRAM space in 2 CAS mode.
Output
Lower column address strobe signal
when accessing 16-bit DRAM
space.
Row address strobe when area 2
set as DRAM space.
Row address strobe when area 3
set as DRAM space.
Row address strobe when area 4
set as DRAM space.
Row address strobe when area 5
set as DRAM space.
Output
Upper column address strobe when
accessing DRAM space.
Input
Wait request signal
Output
Multiplexed output of row address
and column address.
Input/output Data input/output pin.
Output
Output enable signal when
accessing DRAM space in read
mode.
(precharge cycle) 1 state, T
P
(row address output
r
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