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10.11.2 Register Configuration
Table 10-18 shows the port E register configuration.
Table 10-18 Port E Registers
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit
:
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
R/W
:
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller.
• Mode 7
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
388
Abbreviation
PEDDR
PEDR
PORTE
PEPCR
7
6
0
0
W
W
R/W
W
R/W
R
R/W
5
4
0
0
W
W
Initial Value
H'00
H'00
Undefined
H'00
3
2
0
0
W
W
Address *
H'FE3D
H'FF0D
H'FFBD
H'FE44
1
0
0
0
W
W
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