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Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 11-52 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 11-52 Contention between Buffer Register Write and Compare Match
488
TGR write cycle
T1
T2
Buffer register
address
N
M
N
Buffer register write data
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