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Port A MOS Pull-Up Control Register (PAPCR)
Bit
:
Initial value :
Undefined Undefined Undefined Undefined
R/W
:
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. In
modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI's
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI's SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
PAPCR is initialized by a manual reset or to H'0 (bits 3 to 0) by a power-on reset, and in hardware
standby mode. It retains its prior state in software standby mode.
Port A Open Drain Control Register (PAODR)
Bit
:
Initial value :
Undefined Undefined Undefined Undefined
R/W
:
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA7 to PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
366
7
6
—
—
—
—
7
6
—
—
—
—
5
4
—
—
PA3PCR PA2PCR PA1PCR PA0PCR
—
—
5
4
—
—
PA3ODR PA2ODR PA1ODR PA0ODR
—
—
3
2
0
0
R/W
R/W
3
2
0
0
R/W
R/W
1
0
0
0
R/W
R/W
1
0
0
0
R/W
R/W
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