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Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO,
BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1
makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an
input port.
• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the ø output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
PF7DR
Initial value :
R/W
:
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port F Register (PORTF)
Bit
:
PF7
Initial value :
R/W
:
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state by a manual reset or in
software standby mode.
394
7
6
PF6DR
PF5DR
0
0
R/W
7
6
PF6
—*
—*
R
R
5
4
PF4DR
PF3DR
0
0
R/W
R/W
5
4
PF5
PF4
—*
—*
R
R
3
2
PF2DR
PF1DR
0
0
R/W
R/W
3
2
PF3
PF2
—*
—*
R
R
1
0
PF0DR
0
0
R/W
R/W
1
0
PF1
PF0
—*
—*
R
R
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