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TMDR0—Timer Mode Register 0
TMDR3—Timer Mode Register 3
Channel 0: TMDR0
Channel 3: TMDR3
Bit
:
Initial value
:
R/W
:
Mode 3 to 0
Notes: 1.
7
6
—
—
BFB
1
1
—
—
R/W
Buffer operation B
0
Normal TGRB operation.
1
Buffer operation of TGRB and TGRD.
Buffer operation A
0
1
MD3*
1
MD2*
2
0
0
1
1
*
MD3 is a reserved bit. Only write 0 to this bit.
2.
Phase calculation mode cannot be set for channels 0 and 3.
Only write 0 to MD2.
H'FF11
H'FE81
5
4
BFA
MD3
0
0
R/W
R/W
Normal TGRA operation.
Buffer operation of TGRA and TGRC.
MD1
MD0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
0
0
Phase calculation mode 1
1
Phase calculation mode 2
1
0
Phase calculation mode 3
1
Phase calculation mode 4
*
*
—
3
2
MD2
MD1
0
0
R/W
R/W
* : Don't care
TPU0
TPU3
1
0
MD0
0
0
R/W
1047
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