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7.3.4
Interface Specifications for Each Area
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (7.4, 7.5 and 7.7) should be referred to for further
details.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
A CS0 signal can be output when accessing area 0 external space.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space.
CS1 and CS6 pin signals can be output when accessing the area 1 and 6 external space.
Only the basic bus interface can be used for areas 1 and 6.
Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space.
CS2 to CS5 signals can be output when accessing area 2 to 5 external space.
The standard bus interface or DRAM interface can be selected for areas 2 to 5. In DRAM interface
mode, signals CS2 to CS5 are used as RAS signals.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
A CS7 signal can be output when accessing area 7 external space.
Only the basic bus interface can be used for the area 7.
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