Hitachi H8S/2633 Hardware Manual page 508

Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 11-49 shows the timing in this case.
ø
Address
Write signal
Counter clear
signal
TCNT
Figure 11-49 Contention between TCNT Write and Clear Operations
TCNT write cycle
T1 T2
TCNT address
N H'0000
485