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TIOR4—Timer I/O Control Register 4
Bit
:
IOB3
Initial value
:
R/W
:
R/W
TGR4B I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
7
6
IOB2
IOB1
0
0
R/W
R/W
TGR4A I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
TGR4B is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR4B is
Capture input
input
source is
capture
TIOCB4 pin
register
Capture input
source is TGR3C
compare match/
input capture
H'FE92
5
4
IOB0
IOA3
0
0
R/W
R/W
TGR4A is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR4A is
Capture input
input
source is
capture
TIOCA4 pin
register
Capture input
source is TGR3A
compare match/
input capture
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of TGR3C
compare match/input capture
3
2
IOA2
IOA1
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of TGR3A
compare match/input capture
*: Don't care
TPU4
1
0
IOA0
0
0
R/W
*: Don't care
1049
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