Hitachi H8S/2633 Hardware Manual page 795

When the RAME bit is set to 1, accesses to addresses H'FFB000 to H'FFEFBF and H'FFFFC0 to

H'FFFFFF in the H8S/2633, to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in

the H8S/2632, and to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the

H8S/2631, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip

address space is accessed.

Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to

and read in byte or word units. Each type of access can be performed in one state.

Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start

at an even address.

When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to

H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0.

Reserved Areas: Addresses H'FFB000 to H'FFBFFF in the H8S/2632, and H'FFB000 to

H'FFCFFF in the H8S/2631 are reserved areas that cannot be read or written to. When the RAME

bit is cleared to 0, the off-chip address space is accessed.