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Bit 5
IRTR
Description
0
Waiting for transfer, or transfer in progress
[Clearing conditions]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
1
Continuous transfer state
[Setting condition]
•
2
In I
When the TDRE or RDRF flag is set to 1 when AASX = 1
•
In other modes
When the TDRE or RDRF flag is set to 1
Bit 4—Second Slave Address Recognition Flag (AASX): In I
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
Description
0
Second slave address not recognized
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
1
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode and FSX = 0
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
2
I
C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
nearly the same time, if the I
to 1 to indicate that the bus has been taken by another master.
C bus interface slave mode
2
C bus interface detects data differing from the data it sent, it sets AL
2
C bus format slave receive mode,
(Initial value)
(Initial value)
713
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