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Hitachi H8S/2633 Hardware Manual page 160

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7.1.3
Pin Configuration
Table 7-1 summarizes the pins of the bus controller.
Table 7-1
Bus Controller Pins
Name
Address strobe
Read
High write/
write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row
address strobe 2
Chip select 3/row
address strobe 3
Chip select 4/row
address strobe 4
Chip select 5/row
address strobe 5
Chip select 6
Chip select 7
Upper column
address strobe
Lower column
strobe
134
Symbol
I/O
AS
Output
RD
Output
HWR
Output
LWR
Output
CS0
Output
CS1
Output
CS2
Output
CS3/OE
Output
CS4
Output
CS5
Output
CS6
Output
CS7
Output
CAS
Output
LCAS
Output
Function
Strobe signal indicating that address output on address
bus is enabled.
Strobe signal indicating that external space is being
read.
Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled.
Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is enabled.
Strobe signal showing selection of area 0
Strobe signal showing selection of area 1
Strobe signal showing selection of area 2.
When area 2 is allocated to DRAM space, this is the row
address strobe signal for DRAM.
When areas 2 to 5 are contiguous DRAM space, this is
the row address strobe signal for DRAM.
Strobe signal showing selection of area 3.
When area 3 is allocated to DRAM space, this is the row
address strobe signal for DRAM.
When only area 2 is allocated to DRAM space, or when
areas 2 to 5 are contiguous DRAM space, this is output
enable signal.
Strobe signal showing selection of area 4.
When area 4 is allocated to DRAM space, this is the row
address strobe signal for DRAM.
Strobe signal showing selection of area 5.
When area 5 is allocated to DRAM space, this is the row
address strobe signal for DRAM.
Strobe signal showing selection of area 6.
Strobe signal showing selection of area 7.
2 CAS method DRAM upper column address strobe
signal
DRAM lower column address strobe signal

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