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Write pulse application subroutine
Sub-Routine Write Pulse
Enable WDT
Set PSU1 bit in FLMCR1
Wait (y) µs
tspsu:
Set P1 bit in FLMCR1
tsp10 or tsp30 or tsp200:
Wait (z0) µs or (z1) µs or (z2) µs
Clear P1 bit in FLMCR1
Wait (α) µs
tcp:
Clear PSU1 bit in FLMCR1
Wait (β) µs
Disable WDT
End Sub
Note 6: Programming Time
P1 Bit Set Time (µs)
Number of Writes
Programming
1
2
·
·
·
N1–1
N1
N1+1
N1+2
N1+3
·
·
·
N1+N2–2
N1+N2–1
N1+N2
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area (128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the
subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming
data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths.
When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when
the write pulse is applied.
Reprogram Data Computation Table
Original Data (D)
0
0
1
1
Additional-Programming Data Computation Table
Reprogram Data (X')
810
Increment address
Additional
Programming
z0
z1
z0
z1
·
·
·
·
·
·
z0
z1
z0
z1
z2
—
z2
—
z2
—
·
·
·
·
·
·
z2
—
z2
—
z2
—
Verify Data (V)
Reprogram Data (X)
0
1
1
0
0
1
1
1
Verify Data (V)
Additional-Programming Data (X)
0
0
0
1
1
0
1
1
Figure 22-11 Program/Program-Verify Flowchart
Start of programming
START
Set SWE1 bit in FLMCR1
Wait (× 0) µs
tsswe:
Store 128 bytes of program data in program
data area and reprogram data area
n = 1
m = 0
Successively write 128-byte reprogram
data to flash memory
Sub-Routine-Call
Write pulse application subroutine
Set PV1 bit in FLMCR1
Wait (γ) µs
tspv:
H'FF dummy write to verify address
Wait (ε) µs
tspur:
Read verify data
Program data =
verify data?
OK
NG
N1 ≥ 0 ?
OK
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram data area
128-byte data
verification completed?
NG
OK
Clear PV1 bit in FLMCR1
Wait (η) µs
tcpv:
tcpv:
NG
N1 ≥ 0 ?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Additional programming subroutine
NG
m = 0 ?
OK
Clear SWE1 bit in FLMCR1
Wait (×1) µs
tcswe:
tcswe:
End of programming
Comments
Programming complete
Programming is incomplete: reprogramming should be performed
Left in the erased state
0
Additional programming should be performed
1
Additional programming should not be performed
1
Additional programming should not be performed
1
Additional programming should not be performed
Programming must be executed in the erased state.
Do not perform additional programming on addresses
that have already been programmed.
*
4
*
1
*
2
n ← n + 1
NG
m = 1
*
4
*
3
*
4
*
1
NG
n ≥ (N1 + N2) ?
OK
Clear SWE1 bit in FLMCR1
Wait (×1) µs
tcswe:
Programming failure
Comments
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