Hitachi H8S/2633 Hardware Manual page 207

(address shift set to 10 bits)

Figure 7-21 Example Connection of EDO Page Mode DRAM (OES=1)

Burst Operation

In addition to full DRAM access (normal DRAM access), in which the row address is output each

time the data in DRAM is accessed, there is also a high-speed page mode that allows high-speed

access (burst access). In this method, if the same row address is accessed successively, the row

address is output once and then only the column address is changed. Burst access is selected by

setting the BE bit of the MCR to 1.

2CAS 16Mbit DRAM

1MB × 16-bit configuration

10-bit column address

(Row address input: A9 to A0)

(Column address input: A9 to A0)