Hitachi H8S/2633 Hardware Manual page 318

Figure 8-42 shows an example in which a low level is not output at the TEND pin.

Internal address

Internal read signal

Internal write signal

External address

Figure 8-42 Example in Which Low Level is Not Output at TEND Pin

Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in

synchronization with DMAC internal operations. The operation is as follows:

[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches

[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].

[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and

switches to [1].

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer

is enabled is performed by detection of a low level.

Activation Source Acceptance: At the start of activation source acceptance, a low level is

detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an

internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an

internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to

enable transfer.

When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ

pin low level remaining from the end of the previous transfer, etc.

External write by CPU, etc.