Hitachi H8S/2633 Hardware Manual page 174

Bit 3 Bit 2 Bit 1
AE3 AE2 AE1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to
1.
148
Bit 0
AE0 Description
0 A8–A23 address output disabled
1 A8 address output enabled; A9–A23 address output disabled
0 A8, A9 address output enabled; A10–A23 address output
disabled
1 A8–A10 address output enabled; A11–A23 address output
disabled
0 A8–A11 address output enabled; A12–A23 address output
disabled
1 A8–A12 address output enabled; A13–A23 address output
disabled
0 A8–A13 address output enabled; A14–A23 address output
disabled
1 A8–A14 address output enabled; A15–A23 address output
disabled
0 A8–A15 address output enabled; A16–A23 address output
disabled
1 A8–A16 address output enabled; A17–A23 address output
disabled
0 A8–A17 address output enabled; A18–A23 address output
disabled
1 A8–A18 address output enabled; A19–A23 address output
disabled
0 A8–A19 address output enabled; A20–A23 address output
disabled
1 A8–A20 address output enabled; A21–A23 address output
disabled
0 A8–A21 address output enabled; A22, A23 address output
disabled
1 A8–A23 address output enabled
(Initial value*)
(Initial value*)