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21.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21-1 shows the address and initial value of
SYSCR.
Table 21-1 RAM Register
Name
System control register
Note: * Lower 16 bits of the address.
21.2
Register Descriptions
21.2.1
System Control Register (SYSCR)
Bit
:
MACS
Initial value
:
R/W
:
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Note: When the DTC is used, the RAME bit must not be cleared to 0.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
778
Abbreviation
SYSCR
7
6
—
INTM1
0
0
—
R/W
R/W
R/W
5
4
INTM0
NMIEG
0
0
R/W
R/W
Initial Value
H'01
3
2
MRESE
0
0
R/W
Address*
H'FDE5
1
0
—
RAME
0
1
—
R/W
(Initial value)
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