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6.1.3
Register Configuration
Table 6-1 shows the PC break controller registers.
Table 6-1
PC Break Controller Registers
Name
Break address register A
Break address register B
Break control register A
Break control register B
Module stop control register C
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
6.2
Register Descriptions
6.2.1
Break Address Register A (BARA)
31
Bit
:
• • •
—
• • •
Initial value :
Unde-
• • •
fined
R/W
: —
• • •
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a power-on reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23–BAA0): These bits hold the channel A PC
break address.
Abbreviation
BARA
BARB
BCRA
BCRB
MSTPCRC
24
23
22
21
20
BAA
BAA
BAA
BAA
—
23
22
21
20
Unde-
0
0
0
0
fined
—
R/W
R/W
R/W
R/W
Power-On
R/W
Reset
R/W
H'XX000000 Retained
R/W
H'XX000000 Retained
2
R/(W)*
H'00
2
R/(W)*
H'00
R/W
H'FF
19
18
17
16
• • •
BAA
BAA
BAA
BAA
• • •
19
18
17
16
0
0
0
0
• • •
R/W
R/W
R/W
R/W
• • •
Initial Value
Manual
Reset
Retained
Retained
Retained
7
6
5
4
3
BAA
BAA
BAA
BAA
BAA
7
6
5
4
3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
1
Address*
H'FE00
H'FE04
H'FE08
H'FE09
H'FDEA
2
1
0
BAA
BAA
BAA
2
1
0
0
0
0
R/W
R/W
R/W
121
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