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9.2.6
DTC Transfer Count Register B (CRB)
Bit
:
15
Initial value
:
Unde-
fined
—
R/W
:
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
9.2.7
DTC Enable Registers (DTCER)
Bit
:
DTCE7
Initial value
:
R/W
:
R/W
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERF
and DTCERI, with bits corresponding to the interrupt sources that can control enabling and
disabling of DTC activation. These bits enable or disable DTC service for the corresponding
interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
Description
0
DTC activation by this interrupt is disabled
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
1
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 9-4, together with the vector number
generated for each interrupt controller.
302
14
13
12
11
Unde-
Unde-
Unde-
Unde-
fined
fined
fined
fined
—
—
—
—
7
6
DTCE6
DTCE5
0
0
R/W
10
9
8
7
Unde-
Unde-
Unde-
Unde-
fined
fined
fined
fined
—
—
—
—
5
4
DTCE4
DTCE3
0
0
R/W
R/W
6
5
4
Unde-
Unde-
Unde-
Unde-
fined
fined
fined
fined
—
—
—
3
2
DTCE2
DTCE1
0
0
R/W
R/W
3
2
1
0
Unde-
Unde-
Unde-
fined
fined
fined
—
—
—
—
1
0
DTCE0
0
0
R/W
R/W
(Initial value)
(n = 7 to 0)
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