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Hitachi H8S/2633 Hardware Manual page 545

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13.1.4
Register Configuration
Table 13-2 summarizes the registers of the 8-bit timer module.
Table 13-2 8-Bit Timer Registers
Channel
Name
0
Timer control register 0
Timer control/status register 0 TCSR0
Time constant register A0
Time constant register B0
Timer counter 0
1
Timer control register 1
Timer control/status register 1 TCSR1
Time constant register A1
Time constant register B1
Timer counter 1
2
Timer control register 2
Timer control/status register 2 TCSR2
Time constant register A2
Time constant register B2
Timer counter 2
3
Timer control register 3
Timer control/status register 3 TCSR3
Time constant register A3
Time constant register B3
Timer counter 3
All
Module stop control register A MSTPCRA
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 (channel 2) and channel 1 (channel 3) is a 16-bit register with
the upper 8 bits for channel 0 (channel 2) and the lower 8 bits for channel 1 (channel 3), so they
can be accessed together by word transfer instruction.
524
Abbreviation
R/W
TCR0
R/W
R/(W)*
TCORA0
R/W
TCORB0
R/W
TCNT0
R/W
TCR1
R/W
R/(W)*
TCORA1
R/W
TCORB1
R/W
TCNT1
R/W
TCR2
R/W
R/(W)*
TCORA2
R/W
TCORB2
R/W
TCNT2
R/W
TCR3
R/W
R/(W)*
TCORA3
R/W
TCORB3
R/W
TCNT3
R/W
R/W
Initial value
Address*
H'00
H'FF68
2
H'00
H'FF6A
H'FF
H'FF6C
H'FF
H'FF6E
H'00
H'FF70
H'00
H'FF69
2
H'10
H'FF6B
H'FF
H'FF6D
H'FF
H'FF6F
H'00
H'FF71
H'00
H'FDC0
2
H'00
H'FDC2
H'FF
H'FDC4
H'FF
H'FDC6
H'00
H'FDC8
H'00
H'FDC1
2
H'10
H'FDC3
H'FF
H'FDC5
H'FF
H'FDC7
H'00
H'FDC9
H'3F
H'FDE8
1

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