Hitachi H8S/2633 Hardware Manual page 733

Bit 1—General Call Address Recognition Flag (ADZ): In I

this flag is set to 1 if the first frame following a start condition is the general call address (H'00).

ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ

is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive

General call address not recognized

[Clearing conditions]

1. When ICDR data is written (transmit mode) or read (receive mode)

2. When 0 is written in ADZ after reading ADZ = 1

3. In master mode

General call address recognized

[Setting condition]

When the general call address is detected in slave receive mode and

(FSX = 0 or FS = 0)

Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the

receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In

receive mode, after data has been received, the acknowledge data set in this bit is sent to the

transmitting device.

When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line

(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal

software is read.

Receive mode: 0 is output at acknowledge output timing

Transmit mode: Indicates that the receiving device has acknowledged the data (signal

Receive mode: 1 is output at acknowledge output timing

Transmit mode: Indicates that the receiving device has not acknowledged the data

(signal is 1)

C bus format slave receive mode,

(Initial value)