Hitachi H8S/2633 Hardware Manual page 1069

TSR0—Timer Status Register 0

TSR3—Timer Status Register 3

Channel 0: TSR0

Channel 3: TSR3

Initial value

Input capture/output compare flag D

Note: * Only 0 can be written to these bits (to clear these flags).

Overflow flag

Writing 0 to TCFV after reading TCFV=1.

When the TCNT value overflows (H'FFFF → H'0000).

(1) When the DTC is started by a TGID interrupt and the DTC MRB

DISEL bit is 0;

(2) Writing 0 to TGFD after reading TGFD=1.

(1) When TGRD is functioning as the output compare register and

(2) When TGRD is functioning as the input capture register and the value

of TCNT is sent to TGRD by the input capture signal.

Input capture/output compare flag C

(1) When the DTC is started by a TGIC interrupt and the DTC MRB

DISEL bit is 0;

(2) Writing 0 to TGFC after reading TGFC=1.

(1) When TGRC is functioning as the output compare register and

(2) When TGRC is functioning as the input capture register and the value

of TCNT is sent to TGRC by the input capture signal.

Input capture/output compare flag B

(1) When the DTC is started by a TGIB interrupt and the DTC MRB

DISEL bit is 0;

(2) Writing 0 to TGFB after reading TGFB=1.

(1) When TGRB is functioning as the output compare register and

(2) When TGRB is functioning as the input capture register and the value

of TCNT is sent to TGRB by the input capture signal.

Input capture/output compare flag A

(1) When the DTC is started by a TGIA interrupt and the DTC MRB

(2) When the DMAC is started by a TGIA interrupt and the D MAC

(3) Writing 0 to TGFA after reading TGFA=1.

(1) When TGRA is functioning as the output compare register and

(2) When TGRA is functioning as the input capture register and the value

DISEL bit is 0;

DMABCR DTA bit is 1;

of TCNT is sent to TGRA by the input capture signal.