Hitachi H8S/2633 Hardware Manual page 451

Bit 3 Bit 2 Bit 1 Bit 0
Channel IOA3 IOA2 IOA1 IOA0 Description
1 0 0
1
1 0
1
Bit 3 Bit 2 Bit 1 Bit 0
Channel IOA3 IOA2 IOA1 IOA0 Description
2 0 0
1
1 *
428
0 0 TGR1A is Output disabled
output
1
compare
0
1
register
1
0 0
1
1 0
1
0 0 TGR1A is
input
1
capture
*
1
register
* *
0 0 TGR2A is Output disabled
output
1
compare
0
1
register
1
0 0
1
1 0
1
0 0 TGR2A is
input
1
capture
*
1
register
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCA1 pin
Input capture at both edges
Capture input Input capture at generation of
source is TGR0A channel 0/TGR0A compare
compare match/ match/input capture
input capture
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCA2 pin
Input capture at both edges
(Initial value)
*: Don't care
(Initial value)
*: Don't care