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8.3.5
DMA Band Control Register (DMABCR)
Bit
:
DMABCRH :
FAE1
Initial value :
R/W
:
R/W
Bit
:
DMABCRL :
DTME1
Initial value :
R/W
:
R/W
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15
FAE1
Description
0
Short address mode
1
Full address mode
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14
FAE0
Description
0
Short address mode
1
Full address mode
15
14
FAE0
0
0
R/W
7
6
DTE1
DTME0
0
0
R/W
13
12
—
—
0
0
R/W
R/W
5
4
DTE0
DTIE1B
0
0
R/W
R/W
11
10
DTA1
—
0
0
R/W
R/W
3
2
DTIE1A
0
0
R/W
R/W
9
8
DTA0
—
0
0
R/W
R/W
1
0
DTIE0B
DTIE0A
0
0
R/W
R/W
(Initial value)
(Initial value)
231
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