Hitachi H8S/2633 Hardware Manual page 483

Examples of Cascaded Operation: Figure 11-22 illustrates the operation when counting upon

TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated

as input capture registers, and TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.

Figure 11-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been

set for TCNT1, and phase counting mode has been designated for channel 2.

TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.

Figure 11-22 Example of Cascaded Operation (1)

Figure 11-23 Example of Cascaded Operation (2)