Hitachi H8S/2633 Hardware Manual page 497

Table 11-13 TPU Interrupts
Interrupt
Channel Source
0 TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
1 TGI1A
TGI1B
TCI1V
TCI1U
2 TGI2A
TGI2B
TCI2V
TCI2U
3 TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
4 TGI4A
TGI4B
TCI4V
TCI4U
5 TGI5A
TGI5B
TCI5V
TCI5U
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
474
Description
TGR0A input capture/compare match Possible
TGR0B input capture/compare match Not possible Possible
TGR0C input capture/compare match Not possible Possible
TGR0D input capture/compare match Not possible Possible
TCNT0 overflow
TGR1A input capture/compare match Possible
TGR1B input capture/compare match Not possible Possible
TCNT1 overflow
TCNT1 underflow
TGR2A input capture/compare match Possible
TGR2B input capture/compare match Not possible Possible
TCNT2 overflow
TCNT2 underflow
TGR3A input capture/compare match Possible
TGR3B input capture/compare match Not possible Possible
TGR3C input capture/compare match Not possible Possible
TGR3D input capture/compare match Not possible Possible
TCNT3 overflow
TGR4A input capture/compare match Possible
TGR4B input capture/compare match Not possible Possible
TCNT4 overflow
TCNT4 underflow
TGR5A input capture/compare match Possible
TGR5B input capture/compare match Not possible Possible
TCNT5 overflow
TCNT5 underflow
DMAC DTC
Activation Activation
Possible
Not possible Not possible
Possible
Not possible Not possible
Not possible Not possible
Possible
Not possible Not possible
Not possible Not possible
Possible
Not possible Not possible
Possible
Not possible Not possible
Not possible Not possible
Possible
Not possible Not possible
Not possible Not possible
Priority
High
Low