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ICDR using the timing shown in figure 18-6. The selected slave device (i.e. the slave device
with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
(4) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. If the TDRE internal flag has been set to 1, after one frame has been
transmitted SCL is automatically fixed low in synchronization with the internal clock until the
next transmit data is written.
(5) To continue transfer, write the next data to be transmitted into ICDR. After the data has been
transferred to ICDRS and the TDRE internal flag has been set to 1, clear the IRIC flag to 0.
Transmission of the next frame is performed in synchronization with the internal clock.
Data can be transmitted sequentially by repeating steps (4) and (5). To end transmission, after
clearing the IRIC flag and transmitting the final data (with no more transmit data in ICDRT), write
H'FF dummy data to ICDR, and then write 0 to BBSY and SCP in ICCR when the IRIC flag is set
again. This changes SDA from low to high when SCL is high, and generates the stop condition.
Start condition issuance
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
IRIC
ICDRT
ICDRS
User processing
[2] Write BBSY = 1
and SCP = 0
(start condition issuance)
Figure 18-6 Example of Master Transmit Mode Operation Timing
1
2
3
Bit 7
Bit 6
Bit 5
Slave address
Interrupt
request
generation
Address + R/W
Address + R/W
[3] ICDR write
(MLS = WAIT = 0)
4
5
6
Slave address
Bit 4
Bit 3
Bit 2
[3] IRIC clearance
7
8
9
Bit 1
Bit 0
[4]
R/W
A
Interrupt request
generation
[5] ICDR write
[5] IRIC clearance
1
2
Bit 7
Bit 6
Data 1
Data 1
Data 1
721
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