Hitachi H8S/2633 Hardware Manual page 809

Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,

when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is

not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the

corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1

and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both

EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written

with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

The flash memory erase block configuration is shown in table 22-4.

Initial value:

Table 22-4 Flash Memory Erase Blocks

Block (Size)

EB0 (4 kbytes)

EB1 (4 kbytes)

EB2 (4 kbytes)

EB3 (4 kbytes)

EB4 (4 kbytes)

EB5 (4 kbytes)

EB6 (4 kbytes)

EB7 (4 kbytes)

EB8 (32 kbytes)

EB9 (64 kbytes)

EB10 (64 kbytes)

EB11 (64 kbytes)

H'000000–H'000FFF

H'001000–H'001FFF

H'002000–H'002FFF

H'003000–H'003FFF

H'004000–H'004FFF

H'005000–H'005FFF

H'006000–H'006FFF

H'007000–H'007FFF

H'008000–H'00FFFF

H'010000–H'01FFFF

H'020000–H'02FFFF

H'030000–H'03FFFF