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BCRL—Bus Control Register L
Bit
:
BRLE
Initial value
:
R/W
:
DACK timing select
1070
7
6
BREQOE
0
0
R/W
R/W
OE select
0
CS3 pin used as port or as CS3 signal output.
1
When only area 2 is set as DRAM, or when
areas 2 to 5 are set as contiguous DRAM space,
the CS3 pin is used as the OE pin.
BREQO pin enable
0
BREQO output disabled. BREQO can be used as an I/O port.
1
BREQO output enabled.
Bus release enable
0
Release of external bus privileges disabled. BREQ,
BACK, and BREQO can be used as I/O ports.
1
Release of external bus privileges enabled.
0
When performing DMAC single address transmission to the
DRAM space, always perform full access. The DACK signal
level changes to LOW from T
1
Burst access is also available when performing DMAC single
address transmission to the DRAM space. The DACK signal
level changes to LOW from T
Read CAS timing select
0
CAS signal output timing is the same when reading and writing.
1
When reading, the CAS signal is asserted one half cycle faster than
when writing.
WAIT pin enable
0
Wait input via WAIT pin disabled. The WAIT pin can be used as an I/O port.
1
Wait input via WAIT pin enabled.
H'FED5
5
4
—
OES
DDS
0
0
—
R/W
R/W
or T
cycle.
r
1
or T
cycle.
C1
2
Write data buffer enable
0
Do not use write data buffer function.
1
Use write data buffer function.
3
2
RCTS
WDBE
1
0
R/W
R/W
Bus Controller
1
0
WAITE
0
0
R/W
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