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PFCR—Pin Function Control Register
Bit
Bit
:
:
7
CSS07
Initial value
Initial value
:
:
0
R/W
R/W
:
:
R/W
Address output enable 3 to 0
AE3
AE2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1.
6
5
CSS36
BUZZE
0
0
R/W
R/W
LCAS output pin select bit
BUZZ output enable
0
1
CS3/CS6 Select
0
Selects CS3.
1
Selects CS6.
CS0/CS7 Select
0
Selects CS0.
1
Selects CS7.
AE1
AE0
0
0
A8 to A23 address output disabled.
0
1
A8 address output enabled. A9 to A23 address output disabled.
1
0
A8 and A9 address output enabled.
A10 to A23 address output disabled.
1
1
A8 to A10 address output enabled. A11 to A23 address output disabled.
0
0
A8 to A11 address output enabled. A12 to A23 address output disabled.
0
1
A8 to A12 address output enabled. A13 to A23 address output disabled.
A8 to A13 address output enabled. A14 to A23 address output disabled.
1
0
A8 to A14 address output enabled. A15 to A23 address output disabled.
1
1
0
0
A8 to A15 address output enabled. A16 to A23 address output disabled.
0
1
A8 to A16 address output enabled. A17 to A23 address output disabled.
1
0
A8 to A17 address output enabled. A18 to A23 address output disabled.
A8 to A18 address output enabled. A19 to A23 address output disabled.
1
1
A8 to A19 address output enabled. A20 to A23 address output disabled.
0
0
0
1
A8 to A20 address output enabled. A21 to A23 address output disabled.
1
0
A8 to A21 address output enabled. A22 and A23 address output disabled.
1
1
A8 to A23 address output enabled.
H'FDEB
4
3
LCASS
AE3
0
1/0
R/W
R/W
0
LCAS signal output from PF2.
1
LCAS signal output from PF6.
Functions as PF1 input pin.
Functions as BUZZ output pin.
2
1
AE2
AE1
1/0
0
R/W
R/W
System
0
AE0
1/0
R/W
1027
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