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Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI input
1
An interrupt is requested at the rising edge of NMI input
Bit 2—Manual Reset Selection Bit (MRESE): Enables or disenables manual reset input. It is
possible to set the P74/TM02/MRES pin to the manual reset input (MRES).
Table 3-3 shows the relationship between the MRES pin power-on reset and manual reset.
Bit 2
MRESE
Description
0
Disenables manual reset.
Possible to use P74/TM02/MRES pin as P74/TM02 input pin.
1
Enables manual reset.
Possible to use P74/TM02/MRES pin as MRES input pin.
Table 3-3
Relationship Between Power-On Reset and Manual Reset
Pin
RES
MRES
0
*
1
0
1
1
Bit 1—Reserved: This bit always read as 0 and cannot be modified.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Note: When the DTC is used, the RAME bit must be set to 1.
70
Reset Type
Power-on reset
Manual reset
Operation state
(Initial value)
(Initial value)
(Initial state)
*: Don't care
(Initial value)
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