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Port A Data Register (PADR)
Bit
:
Initial value :
Undefined Undefined Undefined Undefined
R/W
:
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a powr-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Port A Register (PORTA)
Bit
:
Initial value :
Undefined Undefined Undefined Undefined
R/W
:
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA7 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state by a manual reset or in
software standby mode.
7
6
—
—
—
—
7
6
—
—
—
—
5
4
—
—
PA3DR
—
—
5
4
—
—
—
—
3
2
PA2DR
PA1DR
0
0
R/W
R/W
3
2
PA3
PA2
—*
—*
R
R
1
0
PA0DR
0
0
R/W
R/W
1
0
PA1
PA0
—*
—*
R
R
365
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