Hitachi H8S/2633 Hardware Manual page 568

14.1.2 Block Diagram
Figure 14-1 shows a block diagram of the PWM D/A module.
Clock selection
PWM0
PWM1
Control logic
Legend:
DACR: PWM D/A control register ( 6 bits)
DADRA: PWM D/A data register A (15 bits)
DADRB: PWM D/A data register B (15 bits)
DACNT: PWM D/A counter (14 bits)
548
Internal clock
ø
ø/2
Clock
Basic cycle
compare-match A
Fine-adjustment
pulse addition A
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Basic cycle overflow
Figure 14-1 PWM D/A Block Diagram
Comparator
DADRA
A
Comparator
DADRB
B
DACNT
DACR
Internal data bus
Bus interface
Module data bus