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TIOR3L—Timer I/O Control Register 3L
Bit
:
IOD3
Initial value
:
R/W
:
R/W
TGR3D I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
*
1
*
*
Notes: 1
When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
2
When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
1054
7
6
IOD2
IOD1
0
0
R/W
R/W
TGR3C I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
Note: 1 When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
TGR3D is
Output disabled
output
Initial output is 0
compare
output
2
register*
Output disabled
Initial output is 1
output
TGR3D is
Capture input
input
source is
capture
TIOCD3 pin
2
register*
Capture input
source is channel
4/count clock
H'FE83
5
4
IOD0
IOC3
0
0
R/W
R/W
TGR3C is
Output disabled
output
Initial output is 0
compare
output
1
register*
Output disabled
Initial output is 1
output
TGR3C is
Capture input
input
source is
capture
TIOCC3 pin
1
register*
Capture input
source is channel
4/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
1
count-down*
3
2
IOC2
IOC1
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
*: Don't care
TPU3
1
0
IOC0
0
0
R/W
*: Don't care
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